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Features
* Programmable Audio Output for Interfacing with Common Audio DAC
- PCM Format Compatible - I2S Format Compatible * 8-bit MCU C51 Core-based (FMAX = 20 MHz) * 2304 bytes of Internal RAM * 64K Bytes of Code Memory - Flash: AT89C5132, ROM: AT83C5132(1) * 4K Bytes of Boot Flash Memory (AT89C5132) - ISP: Download from USB or UART to Any External Memory Cards * USB Rev 1.1 Controller - "Full Speed" Data Transmission * Built-in PLL for USB Clock * MultiMedia Card(R) Interface Compatibility * Atmel DataFlash(R) SPI Interface Compatibility * IDE/ATAPI Interface * 2 Channels 10-bit ADC, 8 kHz (8-True Bit) - Battery Voltage Monitoring - Voice Recording Controlled by Software * Up to 44 bits for General-purpose I/Os for - 4-bit Interrupt Keyboard Port for a 4 x n Matrix - SmartMedia(R) Software Interface * Standard Two 16-bit Timers/Counters * Hardware Watchdog Timer * Standard Full Duplex UART with Baud Rate Generator * SPI Master and Slave Modes Controller * Power Management - Power-on Reset - Software Programmable MCU Clock - Idle Mode, Power-down Mode * Operating Conditions - 3V, 10%, 25 mA Typical Operating at 25C - Temperature Range: -40C to +85C * Packages - TQFP80, TQFP64, BGA81(1) - Dice Note: 1. Contact Atmel for availability.
USB Microcontroller with 64K Byetes ROM or Flash
AT83C5132 AT89C5132 Preliminary Summary
Description
The AT8xC5132 devices are mass storage devices controlling data exchange between various Flash modules, HDD and CD-ROM. The AT89C5132 includes 64K Bytes of Flash memory and allows In-System Programming through an embedded 4K Bytes of Boot Flash memory. The AT83C5132 includes 64K Bytes of ROM memory. The AT8xC5132 includes 2304 bytes of RAM memory. The AT8xC5132 provide all the necessary features for man-machine interface like timers, keyboard port, serial or parallel interface (USB, SPI, IDE), ADC input, I2S output, and all external memory interface (NAND or NOR Flash, SmartMedia, MultiMedia, and DataFlash Cards).
Typical Applications
* * * Flash Recorder/Writer PDAs, Camera, Mobile Phone PC Add-on
Rev. 4176A-8051-08/02
Block Diagram
Figure 1. AT8xC5132 Block Diagram
INT0 INT1 VDD VSS UVDD UVSS AVDD AVSS AREF AIN1:0 TXD RXD T0 T1 SS MISO MOSI SCK
1
1 Interrupt Handler Unit Flash ROM 64K Bytes Flash Boot 4K Bytes
1
1
1
1
2
2
2
2
RAM 2304 bytes
10-bit A to D Converter or 10-bit ADC
UART and BRG
Timers 0/1 Watchdog
SPI/DataFlash Controller
C51 (X2 CORE)
8-BIT INTERNAL BUS
Clock and PLL Unit
I2S/PCM Audio Interface
USB Controller
MMC Interface
Keyboard Interface
I/O Ports IDE Interface
FILT
X1
X2
RST
DOUT DCLK DSEL SCLK
D+
D-
MCLK MDAT MCMD
KIN3:0
P0 - P5
Notes:
1. Alternate function of Port 3 2. Alternate function of Port 4
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Pin Configurations
Figure 2. AT8xC5132, 80-pin TQFP Package
P0.6/AD6 P0.7/AD7 P4.3/SS P4.2/SCK P4.1/MOSI P4.0/MISO P2.0/A8 P2.1/A9 P4.7 P4.6 P5.1 P5.0 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 ALE ISP P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P1.3/KIN3 P1.4 P1.5 P1.6 P1.7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
VSS VDD
TQFP80
VDD
PVDD FILT PVSS
VSS
X2 X1 TST UVDD UVSS
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P4.5 P4.4 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15
VSS VDD
MCLK MDAT MCMD RST SCLK DSEL DCLK DOUT
VSS VDD
P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1# P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD AVDD AVSS AREFP AREFN AIN0 AIN1 P5.2 P5.3
VDD VSS
D+ D-
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
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Figure 3. AT8xC5132, 64-pin TQFP
P4.1/MOSI P0.2/AD2 P0.3/AD3 P0.7/AD7 P4.0/MISO P0.6/AD6 P4.2/SCK P0.5/AD5 P0.4/AD4
P4.3/SS
P2.0/A8
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 ISP
P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P1.3/KIN3 P1.4 P1.5 P1.6 P1.7
P2.1/A9 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VSS VDD
P0.0
P0.1
P4.5 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14
P2.7/A15
TQFP64
VSS
VCC MCLK MDAT MCMD RST SCLK
VDD
FILT
VSS
X2 X1 TST UVDD
VSS VDD
17 18 19 20 21 22 23 24 25 26 27 28 29 30 3132
UVSS D+
VDD VSS
P3.5/T5
AVDD
D-
P3.2/INT0
P3.3/INT1 P3.4/TO
P3.0/RXD P3.1/TXD
P3.6/WR
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AT8xC5132
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P3.7/RD
AVSS P5.3
AT8xC5132
Figure 4. AT8xC5132, 84-pin PLCC Package(1)
P0.6/AD6 P0.7/AD7 P4.3/SS P4.2/SCK P4.1/MOSI P4.0/MISO P2.0/A8 P2.1/A9 P4.7 P4.6 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54
NC P5.1 P5.0 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 ALE ISP P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P1.3/KIN3 P1.4 P1.5 P1.6 P1.7 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
VSS VDD
NC P4.5 P4.4 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15
VDD
PVDD FILT PVSS
PLCC84
VSS VDD
MCLK MDAT MCMD RST SCLK DSEL DCLK DOUT
VSS
X2 NC X1 TST UVDD UVSS
VSS VDD
Note:
1. For development board only.
P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD AVDD AVSS AREFP AREFN AIN0 AIN1 P5.2 P5.3 NC
D+ D-
VDD VSS
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
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Pin Description
All AT8xC5132 signals are detailed by functionality in Table 1 through Table 14. Table 1. Ports Signal Description
Signal Name Type Description Port 0 P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. To avoid any parasitic current consumption, floating P0 inputs must be polarized to VDD or VSS. Port 1 P1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 P2 is an 8-bit bidirectional I/O port with internal pull-ups. Alternate Function
P0.7:0
I/O
AD7:0
P1.7:0
I/O
KIN3:0 SCL SDA A15:8 RXD TXD
P2.7:0
I/O
P3.7:0
I/O
Port 3 P3 is an 8-bit bidirectional I/O port with internal pull-ups.
INT0 INT1 T0 T1 WR RD MISO MOSI SCK SS# -
P4.7:0
I/O
Port 4 P4 is an 8-bit bidirectional I/O port with internal pull-ups.
P5.3:0
I/O
Port 5 P5 is a 4-bit bidirectional I/O port with internal pull-ups.
Table 2. Clock Signal Description
Signal Name Type Description Input to the on-chip inverting oscillator amplifier To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, its output is connected to this pin. X1 is the clock source for internal timing. Output of the on-chip inverting oscillator amplifier To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, leave X2 unconnected. PLL Low Pass Filter input FILT receives the RC network of the PLL low pass filter. Alternate Function
X1
I
-
X2
O
-
FILT
I
-
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Table 3. Timer 0 and Timer 1 Signal Description
Signal Name Type Description Timer 0 Gate Input INT0 serves as external run control for Timer 0, when selected by GATE0 bit in TCON register. INT0# I External Interrupt 0 INT0# input sets IE0 in the TCON register. If bit IT0 in this register is set, bit IE0 is set by a falling edge on INT0#. If bit IT0 is cleared, bit IE0 is set by a low level on INT0#. Timer 1 Gate Input INT1 serves as external run control for Timer 1, when selected by GATE1 bit in TCON register. INT1# I External Interrupt 1 INT1# input sets IE1 in the TCON register. If bit IT1 in this register is set, bit IE1 is set by a falling edge on INT1#. If bit IT1 is cleared, bit IE1 is set by a low level on INT1#. Timer 0 External Clock Input When Timer 0 operates as a counter, a falling edge on the T0 pin increments the count. Timer 1 External Clock Input When Timer 1 operates as a counter, a falling edge on the T1 pin increments the count. P3.3 P3.2 Alternate Function
T0
I
P3.4
T1
I
P3.5
Table 4. Audio Interface Signal Description
Signal Name DCLK DOUT DSEL Type O O O Description DAC Data Bit Clock DAC Audio Data DAC Channel Select Signal DSEL is the sample rate clock output. DAC System Clock SCLK is the oversampling clock synchronized to the digital audio data (DOUT) and the channel selection signal (DSEL). Alternate Function -
SCLK
O
-
Table 5. USB Controller Signal Description
Signal Name Type Description USB Positive Data Upstream Port This pin requires an external 1.5 k pull-up to VDD for full speed operation. USB Negative Data Upstream Port Alternate Function
D+
I/O
-
D-
I/O
-
7
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Table 6. MutiMedia Card Interface Signal Description
Signal Name MCLK Type O Description MMC Clock output Data or command clock transfer. MMC Command line Bidirectional command channel used for card initialization and data transfer commands. To avoid any parasitic current consumption, unused MCMD input must be polarized to VDD or VSS. MMC Data line Bidirectional data channel. To avoid any parasitic current consumption, unused MDAT input must be polarized to VDD or VSS. Alternate Function -
MCMD
I/O
-
MDAT
I/O
-
Table 7. UART Signal Description
Signal Name Type Description Receive Serial Data RXD sends and receives data in serial I/O mode 0 and receives data in serial I/O modes 1, 2 and 3. Transmit Serial Data TXD outputs the shift clock in serial I/O mode 0 and transmits data in serial I/O modes 1, 2 and 3. Alternate Function
RXD
I/O
P3.0
TXD
O
P3.1
Table 8. Controller Signal Description
Signal Name Type Description SPI Master Input Slave Output Data Line When in master mode, MISO receives data from the slave peripheral. When in slave mode, MISO outputs data to the master controller. SPI Master Output Slave Input Data Line When in master mode, MOSI outputs data to the slave peripheral. When in slave mode, MOSI receives data from the master controller. SPI Clock Line When in master mode, SCK outputs clock to the slave peripheral. When in slave mode, SCK receives clock from the master controller. SPI Slave Select Line When in controlled slave mode, SS enables the slave mode. Alternate Function
MISO
I/O
P4.0
MOSI
I/O
P4.1
SCK
I/O
P4.2
SS#
I
P4.3
Table 9. Specific Controller
Signal Name SCL Type I/O Description Reserved Do not set this bit. Reserved Do not set this bit. Alternate Function P1.6
SDA
I/O
P1.7
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Table 10. A/D Converter Signal Description
Signal Name AIN1:0 AREFP AREFN Type I I I Description A/D Converter Analog Inputs Analog Positive Voltage Reference Input Analog Negative Voltage Reference Input This pin is internally connected to AVSS. Alternate Function -
Table 11. Keypad Interface Signal Description
Signal Name Type Description Keypad Input Lines Holding one of these pins high or low for 24 oscillator periods triggers a keypad interrupt. Alternate Function
KIN3:0
I
P1.3:0
Table 12. External Access Signal Description
Signal Name Type Description Address Lines Upper address lines for the external bus. Multiplexed higher address and data lines for the IDE interface. Address/Data Lines Multiplexed lower address and data lines for the external memory or the IDE interface. Address Latch Enable Output ALE signals the start of an external bus cycle and indicates that valid address information is available on lines A7:0. An external latch is used to demultiplex the address from address/data bus. ISP Enable Input This signal must be held to GND through a pull-down resistor at the falling reset to force execution of the internal bootloader. Read Signal Read signal asserted during external data memory read operation. Write Signal Write signal asserted during external data memory write operation. Alternate Function
A15:8
I/O
P2.7:0
AD7:0
I/O
P0.7:0
ALE
O
-
ISP
I/O
-
RD
O
P3.7
WR
O
P3.6
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Table 13. System Signal Description
Signal Name Type Description Reset Input Holding this pin high for 64 oscillator periods while the oscillator is running resets the device. The Port pins are driven to their reset conditions when a voltage lower than VIL is applied, whether or not the oscillator is running. This pin has an internal pull-down resistor which allows the device to be reset by connecting a capacitor between this pin and VDD. Asserting RST when the chip is in Idle mode or Power-down mode returns the chip to normal operation. Test Input Test mode entry signal. This pin must be set to VDD. Alternate Function
RST
I
-
TST
I
-
Table 14. Power Signal Description
Signal Name VDD Type PWR Description Digital Supply Voltage Connect these pins to +3V supply voltage. Circuit Ground Connect these pins to ground. Analog Supply Voltage Connect this pin to +3V supply voltage. Analog Ground Connect this pin to ground. PLL Supply voltage Connect this pin to +3V supply voltage. PLL Circuit Ground Connect this pin to ground. USB Supply Voltage Connect this pin to +3V supply voltage. USB Ground Connect this pin to ground. Alternate Function -
VSS
GND
-
AVDD
PWR
-
AVSS
GND
-
PVDD
PWR
-
PVSS
GND
-
UVDD
PWR
-
UVSS
GND
-
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Internal Pin Structure
Table 15. Detailed Internal Pin Structure
Circuit(1) Type Input Pins TST
VDD Watchdog Output P Input/Output
RRST
RST
VSS
2 Osc Periods Latch Output VDD P1 VDD P2 VDD P3 Input/Output N VSS P1 P2(3) P3 P4 P53:0
VDD P Input/Output N VSS VDD P Output N VSS ALE SCLK DCLK DOUT DSEL MCLK P0 MCMD MDAT ISP
D+ D-
Input/Output
D+ D-
Notes:
1. For information on resistors value, input/output levels, and drive capability, refer to the AT8xC5132 full Datasheet. 2. In Port 2, P1 transistor is continuously driven when outputing a high level bit address (A15:8).
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Application Information
Figure 5. AT8xC5132 Typical Application with On-board Atmel DataFlash
Battery
Ref.
VREFP
VREFN
P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P1.3/KIN3 P0.0 P0.1 P0.2 P0.3 X1 X2 P4.2/SCK
AVDD
AIN1
AIN0
VDD
RST
MMC1
MCLK MDAT MCMD
MMC2
AT8xC5132
UVDD D+ DUVSS
USB PORT
P4.0/SI
DOUT DCLK DSEL SCLK
FILT PVSS P4n
P4.1/SO
DataFlash Memories
Audio DAC
Figure 6. AT8xC5132 Typical Application with On-board Atmel DataFlash and LCD
LCD
Battery
Ref.
P1.3 P0.4 P0.5 P0.6 P0.7
AIN1
AIN0
VREFP
VREFN
P1.6 P1.7
AVDD
VDD
RST
AVSS
P1.4
P1.5
VSS
P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P0.0 P0.1 P0.2 P0.3 X1 X2
MCLK MDAT MCMD
MMC1 MMC2
AT8xC5132
UVDD D+ DUVSS
USB PORT
P4.2/SCK
P4.0/SI
DOUT DCLK DSEL SCLK
FILT P4.n PVSS
P4.1/SO
DataFlash Memories
Audio DAC
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AVSS
P1.4
P1.5
VSS
AT8xC5132
Figure 7. AT8xC5132 Typical Application with On-board SSFDC Flash
LCD
Battery
Ref.
P4.0 P4.1 P4.2 P4.4 P4.5 P4.6 P4.7
VREFN
P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P1.3/KIN3 P0.0 P0.1 P0.2 P0.3 X1 X2
VREFP
AVDD
AIN1
AIN0
VDD
RST
MMC1
MCLK MDAT MCMD
MMC2
AT8xC5132
UVDD D+ DUVSS
USB PORT
P3.6/WR#
DOUT DCLK DSEL SCLK
FILT P2 PVSS P0
P3.7/RD#
Audio DAC SSFDC Memories or SmartMedia Cards
SmartMedia
Figure 8. AT8xC5132 Typical Application with IDE CD-ROM Drive
LCD
Battery
Ref.
P4.0 P4.1 P4.2 P4.4 P4.5 P4.6 P4.7
VREFN
VDD
P1.6 P1.7
VREFP
AVDD
AIN1
AIN0
RST
AVSS
P3.4
P3.5
VSS
P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P0.0 P0.1 P0.2 P0.3 X1 X2 P3.6/WR# FILT P2 PVSS P0
MMC1
MCLK MDAT MCMD
MMC2
AT8xC5132
UVDD D+ DUVSS
USB PORT
P3.7/RD#
DOUT DCLK DSEL SCLK
Audio DAC IDE CD-ROM
AVSS
P3.4
P3.5
VSS
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Address Spaces
The AT8xC5132 derivatives implement four different address spaces: * * * * Program/Code Memory Boot Memory Data Memory Special Function Registers (SFRs)
Code Memory
The AT89C5132 and AT83C5132 implement 64K Bytes of on-chip program/code memory. The AT83C5132 product provides the internal program/code memory in ROM technology while the AT89C5132 product provides it in Flash technology. The Flash memory increases ROM functionality by enabling in-circuit electrical erasure and programming. Thanks to the internal charge pump, the high voltage needed for programming or erasing Flash cells is generated on-chip using the standard VDD voltage. Thus, the AT89C5132 can be programmed using only one voltage and allows in application software programming commonly known as IAP. Hardware programming mode is also available using specific programming tools.
Boot Memory
The AT89C5132 implements 4K Bytes of on-chip boot memory provided in Flash technology. This boot memory is delivered programmed with a standard bootloader software allowing in system programming commonly known as ISP. It also contains some Application Programming Interfaces routines commonly known as API allowing user to develop his own bootloader. The AT8xC5132 derivatives implement 2304 bytes of on-chip data RAM. This memory is divided in two separate areas: * * 256 bytes of on-chip RAM memory (standard C51 memory). 2048 bytes of on-chip expanded RAM memory (ERAM accessible via MOVX instructions).
Data Memory
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Special Function Registers
The Special Function Registers (SFRs) of the AT8xC5132 derivatives fall into the categories detailed in Table 16 through Table 31. The relative addresses of these SFRs are provided together with their reset values in Table 32. In this table, the bit-addressable registers are identified by Note 1.
Table 16. C51 Core SFRs
Mnemonic ACC B PSW SP DPL Add Name 7 6 5 4 3 2 1 0 E0h Accumulator F0h D0h 81h 82h B Register Program Status Word Stack Pointer Data Pointer Low byte Data Pointer High byte CY AC F0 RS1 RS0 OV F1 P
DPH
83h
Table 17. System Management SFRs
Mnemonic PCON AUXR AUXR1 NVERS Add 87h Name Power Control 7 SMOD1 NV7 6 SMOD0 EXT16 NV6 5 M0 ENBOOT NV5 4 DPHDIS NV4 3 GF1 XRS1 GF3 NV3 2 GF0 XRS0 0 NV2 1 PD EXTRAM NV1 0 IDL AO DPS NV0
8Eh Auxiliary Register 0 A2h Auxiliary Register 1 FBh Version Number
Table 18. PLL and System Clock SFRs
Mnemonic CKCON PLLCON PLLNDIV PLLRDIV Add 8Fh Name Clock Control 7 R1 R9 6 R0 N6 R8 5 N5 R7 4 N4 R6 3 PLLRES N3 R5 2 N2 R4 1 PLLEN N1 R3 0 X2 PLOCK N0 R2
E9h PLL Control EEh PLL N Divider EFh PLL R Divider
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Table 19. Interrupt SFRs
Mnemonic IEN0 Add A8h Name Interrupt Enable Control 0 Interrupt Enable Control 1 Interrupt Priority Control High 0 Interrupt Priority Control Low 0 Interrupt Priority Control High 1 Interrupt Priority Control Low 1 7 EA 6 EAUD 5 4 ES 3 ET1 2 EX1 1 ET0 0 EX0
IEN1
B1h
-
EUSB
-
EKB
EADC
ESPI
EI2C
EMMC
IPH0
B7h
-
IPHAUD
-
IPHS
IPHT1
IPHX1
IPHT0
IPHX0
IPL0
B8h
-
IPLAUD
-
IPLS
IPLT1
IPLX1
IPLT0
IPLX0
IPH1
B3h
-
IPHUSB
-
IPHKB
IPHADC
IPHSPI
IPHI2C
IPHMMC
IPL1
B2h
-
IPLUSB
-
IPLKB
IPLADC
IPLSPI
IPLI2C
IPLMMC
Table 20. Port SFRs
Mnemonic P0 P1 P2 P3 P4 P5 Add 80h 90h Name 8-bit Port 0 8-bit Port 1 7 6 5 4 3 2 1 0
A0h 8-bit Port 2 B0h 8-bit Port 3 C0h 8-bit Port 4 D8h 4-bit Port 5
-
Table 21. Flash Memory SFR
Mnemonic FCON Add Name 7 FPL3 6 FPL2 5 FPL1 4 FPL0 3 FPS 2 FMOD1 1 FMOD0 0 FBUSY D1h Flash Control
Table 22. Timer SFRs
Mnemonic TCON Add 88h Name Timer/Counter 0 and 1 Control Timer/Counter 0 and 1 Modes Timer/Counter 0 Low Byte Timer/Counter 0 High Byte Timer/Counter 1 Low Byte 7 TF1 6 TR1 5 TF0 4 TR0 3 IE1 2 IT1 1 IE0 0 IT0
TMOD
89h
GATE1
C/T1#
M11
M01
GATE0
C/T0#
M10
M00
TL0
8Ah
TH0
8Ch
TL1
8Bh
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Table 22. Timer SFRs (Continued)
Mnemonic TH1 Add 8Dh Name Timer/Counter 1 High Byte WatchDog Timer Reset WatchDog Timer Program WTO2 WTO1 WTO0 7 6 5 4 3 2 1 0
WDTRST
A6h
WDTPRG
A7h
Table 23. Audio Interface SFRs
Mnemonic AUDCON0 AUDCON1 AUDSTA AUDDAT AUDCLK Add Name 7 JUST4 SRC SREQ AUD7 6 JUST3 DRQEN UDRN AUD6 5 JUST2 MSREQ AUBUSY AUD5 4 JUST1 MUDRN AUD4 AUCD4 3 JUST0 AUD3 AUCD3 2 POL DUP1 AUD2 AUCD2 1 DSIZ DUP0 AUD1 AUCD1 0 HLR AUDEN AUD0 AUCD0 9Ah Audio Control 0 9Bh Audio Control 1 9Ch Audio Status 9Dh Audio Data ECh Audio Clock Divider
Table 24. USB Controller SFRs
Mnemonic USBCON USBADDR USBINT USBIEN Add Name 7 USBE FEN 6 SUSPCLK UADD6 5 SDRMWUP UADD5 WUPCPU EWUPCPU 4 UADD4 EORINT EEORINT 3 UPRSM UADD3 SOFINT ESOFINT 2 RMWUPE UADD2 1 CONFG UADD1 0 FADDEN UADD0 SPINT ESPINT BCh USB Global Control C6h USB Address BDh USB Global Interrupt BEh USB Global Interrupt Enable USB Endpoint Number USB Endpoint X Control USB Endpoint X Status
UEPNUM
C7h
-
-
-
-
-
-
EPNUM1
EPNUM0
UEPCONX
D4h
EPEN
-
-
-
DTGL
EPDIR
EPTYPE1
EPTYPE0
UEPSTAX UEPRST UEPINT
CEh
DIR -
-
STALLRQ -
TXRDY -
STLCRC EP3RST EP3INT
RXSETUP EP2RST EP2INT
RXOUT EP1RST EP1INT
TXCMP EP0RST EP0INT
D5h USB Endpoint Reset F8h USB Endpoint Interrupt USB Endpoint Interrupt Enable USB Endpoint X Fifo Data USB Endpoint X Byte Counter USB Frame Number Low
UEPIEN
C2h
-
-
-
-
EP3INTE
EP2INTE
EP1INTE
EP0INTE
UEPDATX
CFh
FDAT7
FDAT6
FDAT5
FDAT4
FDAT3
FDAT2
FDAT1
FDAT0
UBYCTX
E2h
-
BYCT6
BYCT5
BYCT4
BYCT3
BYCT2
BYCT1
BYCT0
UFNUML
BAh
FNUM7
FNUM6
FNUM5
FNUM4
FNUM3
FNUM2
FNUM1
FNUM0
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Table 24. USB Controller SFRs
Mnemonic UFNUMH USBCLK Add BBh Name USB Frame Number High 7 6 5 CRCOK 4 CRCERR 3 2 FNUM10 1 FNUM9 USBCD1 0 FNUM8 USBCD0
EAh USB Clock Divider
Table 25. MMC Controller SFRs
Mnemonic MMCON0 MMCON1 MMCON2 MMSTA MMINT MMMSK MMCMD MMDAT MMCLK Add Name 7 DRPTR BLEN3 MMCEN MCBI MCBM MC7 MD7 MMCD7 6 DTPTR BLEN2 DCR EORI EORM MC6 MD6 MMCD6 5 CRPTR BLEN1 CCR CBUSY EOCI EOCM MC5 MD5 MMCD5 4 CTPTR BLEN0 CRC16S EOFI EOFM MC4 MD4 MMCD4 3 MBLOCK DATDIR DATFS F2FI F2FM MC3 MD3 MMCD3 2 DFMT DATEN DATD1 CRC7S F1FI F1FM MC2 MD2 MMCD2 1 RFMT RESPEN DATD0 RESPFS F2EI F2EM MC1 MD1 MMCD1 0 CRCDIS CMDEN FLOWC CFLCK F1EI F1EM MC0 MD0 MMCD0
E4h MMC Control 0 E5h MMC Control 1 E6h MMC Control 2 DEh MMC Control and Status
E7h MMC Interrupt DFh MMC Interrupt Mask
DDh MMC Command DCh MMC Data EDh MMC Clock Divider
Table 26. IDE Interface SFR
Mnemonic DAT16H Add F9h Name High Order Data Byte 7 D15 6 D14 5 D13 4 D12 3 D11 2 D10 1 D9 0 D8
Table 27. Serial I/O Port SFRs
Mnemonic SCON SBUF SADEN SADDR BDRCON BRL Add 98h 99h B9h A9h 92h 91h Name Serial Control Serial Data Buffer Slave Address Mask Slave Address Baud Rate Control Baud Rate Reload BRR TBCK RBCK SPD SRC 7 FE/SM0 6 SM1 5 SM2 4 REN 3 TB8 2 RB8 1 TI 0 RI
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Table 28. SPI Controller SFRs
Mnemonic SPCON SPSTA SPDAT Add Name 7 SPR2 SPIF SPD7 6 SPEN WCOL SPD6 5 SSDIS SPD5 4 MSTR MODF SPD4 3 CPOL SPD3 2 CPHA SPD2 1 SPR1 SPD1 0 SPR0 SPD0 C3h SPI Control C4h SPI Status C5h SPI Data
Table 29. Specific Controller
Mnemonic SSCON SSSTA SSDAT SSADR Add 93h 94h 95h 96h Name Reserved Reserved Reserved Reserved 7 SSCR2 SSC4 SSD7 SSA7 6 SSPE SSC3 SSD6 SSA6 5 SSSTA SSC2 SSD5 SSA5 4 SSSTO SSC1 SSD4 SSA4 3 SSI SSC0 SSD3 SSA3 2 SSAA 0 SSD2 SSA2 1 SSCR1 0 SSD1 SSA1 0 SSCR0 0 SSD0 SSGC
Table 30. Keyboard Interface SFRs
Mnemonic KBCON KBSTA Add Name 7 KINL3 KPDE 6 KINL2 5 KINL1 4 KINL0 3 KINM3 KINF3 2 KINM2 KINF2 1 KINM1 KINF1 0 KINM0 KINF0 A3h Keyboard Control A4h Keyboard Status
Table 31. A/D Controller SFRs
Mnemonic ADCON ADCLK ADDL ADDH Add F3h F2h F4h F5h Name ADC Control ADC Clock Divider ADC Data Low Byte ADC Data High Byte 7 ADAT9 6 ADIDL ADAT8 5 ADEN ADAT7 4 ADEOC ADCD4 ADAT6 3 ADSST ADCD3 ADAT5 2 ADCD2 ADAT4 1 ADCD1 ADAT1 ADAT3 0 ADCS ADCD0 ADAT0 ADAT2
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Table 32. SFR Addresses and Reset Values
0/8 F8h UEPINT 0000 0000 B(1) 0000 0000 PLLCON 0000 1000 ACC(1) 0000 0000 P5(1) XXXX 1111 PSW1 0000 0000 FCON(3) 1111 0000(4) 1/9 DAT16H XXXX XXXX ADCLK 0000 0000 USBCLK 0000 0000 UBYCTLX 0000 0000 2/A 3/B NVERS(2) 1000 0010 ADCON 0000 0000 ADDL 0000 0000 AUDCLK 0000 0000 MMCON0 0000 0000 MMDAT 1111 1111 UEPCONX 0000 0000 ADDH 0000 0000 MMCLK 0000 0000 MMCON1 0000 0000 MMCMD 1111 1111 UEPRST 0000 0000 UEPSTAX 0000 0000 P4(1) 1111 1111 IPL0(1) X000 0000 P3(1) 1111 1111 IEN0(1) 0000 0000 P2(1) 1111 1111 SCON 0000 0000 P1(1) 1111 1111 TCON(1) 0000 0000 P0(1) 1111 1111 0/8 Reserved SBUF XXXX XXXX BRL 0000 0000 TMOD 0000 0000 SP 0000 0111 1/9 SADEN 0000 0000 IEN1 0000 0000 SADDR 0000 0000 AUXR1 XXXX 00X0 AUDCON0 0000 1000 BDRCON XXX0 0000 TL0 0000 0000 DPL 0000 0000 2/A KBCON 0000 1111 AUDCON1 1011 0010 SSCON 0000 0000 TL1 0000 0000 DPH 0000 0000 3/B 4/C 5/D 6/E KBSTA 0000 0000 AUDSTA 1100 0000 SSSTA 1111 1000 TH0 0000 0000 AUDDAT 1111 1111 SSDAT 1111 1111 TH1 0000 0000 SSADR 1111 1110 AUXR X000 1101 CKCON 0000 000X(5) PCON XXXX 0000 7/F WDTRST XXX XXXX WDTPRG XXXX X000 UEPIEN 0000 0000 UFNUML 0000 0000 IPL1 0000 0000 SPCON 0001 0100 UFNUMH 0000 0000 IPH1 0000 0000 SPSTA 0000 0000 USBCON 0000 0000 SPDAT XXXX XXXX USBINT 0000 0000 USBADDR 1000 0000 USBIEN 0001 0000 IPH0 X000 0000 UEPDATX 0000 0000 UEPNUM 0000 0000 PLLNDIV 0000 0000 MMCON2 0000 0000 MMSTA 0000 0000 PLLRDIV 0000 0000 MMINT 0000 0011 MMMSK 1111 1111 4/C 5/D 6/E 7/F FFh
F0h
F7h
E8h
EFh
E0h
E7h
D8h
DFh
D0h
D7h
C8h
CFh
C0h
C7h
B8h
BFh
B0h
B7h
A8h
AFh
A0h
A7h
98h
9Fh
90h
97h
88h
8Fh
80h
87h
Notes:
1. 2. 3. 4. 5.
SFR registers with least significant nibble address equal to 0 or 8 are bit-addressable. NVERS reset value depends on the silicon version. FCON register is only available in AT89C5132 product. FCON reset value is 00h in case of reset with hardware condition. CKCON reset value depends on the X2B bit (programmed or unprogrammed) in the Hardware Byte.
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In-System and In-Application Programming
In-System Programming
Hardware Boot Process As described in the section "Program/Code Memory" of the AT8xC5132 datasheet, The AT89C5132 implements a 4K Bytes Flash boot memory. This boot memory is delivered programmed with a standard bootloader software allowing In-System Programming (ISP). It also contains some Application Programming Interface routines named API routines allowing In Application Programming (IAP) by using user's own bootloader. The ISP boot process is divided in two different processes: the hardware and software boot process detailed in the following sections. As detailed in Figure 9, there are two hardware conditions that allow the user to execute the bootloader: the hardware and the programmed conditions. The hardware condition is based on the ISP pin. When driving this pin to low level, the chip reset forces the execution of the bootloader software. The hardware condition takes precedence on the programmed condition and always allows in-system recovery when the user's memory has been corrupted. Programmed Condition The programmed condition is based on the Bootloader Jump Bit (BLJB) in the hardware security bytes (HSB). When this bit is programmed (by hardware or software programming mode), the chip reset forces the execution of the bootloader software. Whatever the physical medium may be, the bootloader software always starts execution by testing FCON to know if execution comes from hardware or programmed condition. If it is from hardware condition, Atmel's bootloader is executed. If it is from programmed condition, the Software Boot Vector (SBV) is used to build a 16-bit address, SBV content being the MSB and the LSB at 00h. If this address is valid (< F000h), a jump occurs at this address to execute the user's bootloader. Otherwise, jump is performed to Atmel's bootloader. This implies that the user's bootloader does not execute any code mapped from F000h to FFFFh.
Hardware Condition
Software Boot Process
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Figure 9. Boot Process Algorithm
RESET
Hard Cond? ISP= L?
Hardware Process
Prog Cond? BLJB= P?
Hard Cond Init ENBOOT = 1 PC= F000h FCON= 00h
Standard Init ENBOOT = 0 PC = 0000h FCON = F0h
Prog Cond Init ENBOOT= 1 PC = F000h FCON = F0h
Hard Cond? FCON = 00h?
Software Process
User Vector? SBV< F0h?
User Init PCH= SBV PCL= 00h
User's Application
User's Bootloader
Atmel's Bootloader
In-Application Programming
The IAP is based on several Application Program Interface routines (APIs) that may be called by the user's bootloader to allow programming of the Flash memory.
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Peripherals
The AT8xC5132 peripherals are briefly described in the following sections. For further details on how to interface (hardware and software) to these peripherals, please refer to the AT8xC5132 complete datasheet. The AT8xC5132 internal clocks are extracted from an on-chip PLL fed by an on-chip oscillator. Four clocks are generated respectively for the C51 core, the audio interface, and the other peripherals. The C51 and peripheral clocks are derived from the oscillator clock. The audio interface sample rates are also obtained by dividing the PLL output clock. The AT8xC5132 implement five 8-bit ports (P0 to P4) and one 4-bit port (P5). In addition to performing general-purpose I/Os, some ports are capable of external data memory operations; others allow for alternate functions. All I/O Ports are bidirectional. Each Port contains a latch, an output driver and an input buffer. Port 0 and Port 2 output drivers and input buffers facilitate external memory operations. Some Port 1, Port 3 and Port 4 pins serve for both general-purpose I/Os and alternate functions. The AT8xC5132 implement the two general-purpose, 16-bit Timers/Counters of a standard C51. They are identified as Timer 0, Timer 1, and can independently be configured each to operate in a variety of modes as a Timer or as an event Counter. When operating as a Timer, a Timer/Counter runs for a programmed length of time, then issues an interrupt request. When operating as a Counter, a Timer/Counter counts negative transitions on an external pin. After a preset number of counts, the Counter issues an interrupt request. The AT8xC5132 implement a hardware Watchdog Timer that automatically resets the chip if it is allowed to time out. The WDT provides a means of recovering from routines that do not complete successfully due to software or hardware malfunctions. The AT8xC5132 implements an audio output interface allowing the decoded audio bitstream to be output in various formats. They are compatible with right and left justification PCM and I2S formats and the on-chip PLL allows connection of almost all commercial audio DAC families available on the market. The AT8xC5132 implements a full-speed Universal Serial Bus Interface. The USB interface can be used for the following purposes: * * Download of files by supporting the USB mass storage class. In-System Programming by supporting the USB firmware upgrade class.
Clock Generator System
Ports
Timers/Counters
Watchdog Timer
Audio Output Interface
Universal Serial Bus Interface
MultiMedia Card Interface
The AT8xC5132 implements a MultiMedia Card (MMC) interface compliant to the V2.2 specification in MultiMedia Card mode. The MMC allows storage of files in removable Flash memory cards that can be easily plugged or removed from the application. It can also be used for In-System Programming. The AT8xC5132 provide an IDE/ATAPI interface allowing connection of devices such as CD-ROM reader, CompactFlashTM cards, Hard Disk Drive, etc. It consists of a 16-bit bidirectional bus part of the low-level ANSI ATA/ATAPI specification. It is provided for mass storage interface but could be used for In-System Programming using CD-ROM.
IDE/ATAPI Interface
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Serial I/O Interface
The AT8xC5132 implement a serial port with its own baud rate generator providing one single synchronous communication mode and three full-duplex UART communication modes. It is provided for the following purposes: * * In-System Programming Remote control of the AT8xC5132 by a host
Serial Peripheral Interface
The AT8xC5132 implement a Serial Peripheral Interface (SPI) supporting master and slave modes. It is provided for the following purposes: * * * Interfacing DataFlash memory and DataFlash cards Remote control of the AT8xC5132 by a host In-System Programming
A/D Controller
The AT8xC5132 implement a 2-channel 10-bit (8 true bits) analog to digital converter (ADC). It is provided for the following purposes: * * * Battery monitoring. Voice recording. Corded remote control.
Keyboard Interface
The AT8xC5132 implements a keyboard interface allowing connection of 4 x n matrix keyboard. It is based on 4 inputs with programmable interrupt capability on both high or low level. These inputs are available as alternate function of P1.3:0 and allow exit from idle and power-down modes.
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